1. Field of the Invention
The present invention generally relates to nonvolatile memory circuits and nonvolatile memory devices, and particularly relates to a nonvolatile memory circuit and nonvolatile memory device that can store data without a power supply voltage applied thereto.
2. Description of the Related Art
Conventionally, nonvolatile memories that can be electrically written and store data even when the power supply is turned off include EEPROM, FeROM, MRAM, etc.
FIG. 1 is a drawing showing a basic construction of an EEPROM memory cell. FIG. 2 is a circuit diagram of an EEPROM memory cell.
As shown in FIG. 1, an EEPROM memory cell 1 has a structure in which a gate electrode 2 called a floating gate electrically insulated from other parts and a gate electrode 3 of a conventional MIS-type transistor called a control gate are stacked one over another (see Patent Document 1, for example). In respect of the memory cell 1, as shown in FIG. 2, the gate electrode 3 is connected to a word line WL, and a source (N+ shown In FIG. 1) and a drain (N+ shown in FIG. 1) formed in a substrate (P-sub shown in FIG. 1) connect between a bit line BL and a plate line PL.
At the time of data writing, electrons generated by the hot-carrier effect are trapped in the floating electrode. At the time of data erasure, electrons are removed from the floating electrode by use of a tunnel current.
Since EEPROM has a special memory cell structure as shown in FIG. 2, a large number of manufacturing steps need to be added to the manufacturing steps of general-purpose logic circuits. Further, the retention of data is dependent on how satisfactory the electrical insulating property of the floating gate is, so that highly accurate management is necessary to monitor the manufacturing steps. Because of these factors, logic integrated circuits having EEPROM implemented thereon are not stable in terms of their yield, and have the problem of high cost.
The same issues also exist in the case of FeRAM and MRAM. The ferroelectric materials used in FeROM and the magnetic materials used in MRAM are not used in the manufacturing of conventional semiconductors. When logic integrated circuits having FeROM or MRAM memory implemented thereon are to be manufactured, thus, there is a need to incorporate the manufacturing steps of forming the memory into the manufacturing steps of the logic integrated circuits. Further, there are enormous difficulties in stabilizing the yield.
Attempts have been made to devise a method by which a nonvolatile memory circuit is obtained by use of the manufacturing steps of general-purpose logic integrated circuits.
FIG. 3 is a drawing showing a circuit configuration of an example of a conventional nonvolatile memory circuit.
A nonvolatile memory circuit 11 shown in FIG. 3 has a flip-flop 12 comprised of transistors PMmn(0+), PMmn(0−), NMmn(0+), and NMmn(0−). A first output terminal of the flip-flop 12 is coupled to a bit line BL+ via a transistor SWmn(o+), and a second output terminal of the flip-flop 12 is coupled to a bit line BL− via a transistor SWmn(o−). The nonvolatile memory circuit 11 is configured such that one bit per cell is stored by causing a hot-carrier-effect-based irreversible degradation to the transistor NMmn(o−) or NMmn(o+), which is one of the NMOS transistors (see Patent Document 1, for example).
FIG. 4 is a timing chart showing the writing of nonvolatile data according to an example of the conventional nonvolatile memory circuit.
When nonvolatile data is to be written, as shown in period T1 of FIG. 4, a power supply line SAM is biased to 5 V, and a power supply line SAP is biased to 1.5 V, for example. The terminals of the transistors NMmn(o+) and NMmn(o−) connected to the power supply line SAN serve as drain terminals.
In this case, the potential Vn(o−) of the bit line BL− is a ground potential, and the potential Vn(o+) of the bit line BL+ is 1.5 V, for example. When the potential Vm(i) of the word line WL is biased to 1.5 V, the transistor SWmn(o+) and the transistor SWmn(o−) are both tuned on. As a result, a higher voltage is applied between the source and drain of the transistor NMmn(o−) than between the source and drain of the transistor NMmn(o+). Since the bit line potential Vn(o−) is the ground potential, and the bit line potential Vn(o+) is 1.5 V, the transistor NMmn(o−) is in the ON state, and the transistor NMmn(o+) is in the OFF state. Due to the effects of these, a strong hot-carrier effect is generated in the transistor NMmn(o−), which results in the transistor NMmn(o−) being degraded to achieve nonvolatile storage.
FIG. 5 is a timing chart showing the reading of nonvolatile data according to an example of the conventional nonvolatile memory circuit.
At time t1, a state transition occurs from the state in which the power supply line SAP and the power supply line SAN are at the same potential to the state in which the power supply line SAP is at a higher potential than is the power supply line SAN. In response, the non-inverted output potential V(o+) and V(o−) of the flip-flop 12 initially in the indeterminate state are latched to become specific potentials. When this happens, a data latch state is restored that corresponds to the unbalance of the transistor NMmn(o−) and the transistor NMmn(o+). In this case, the transistor NMmn(o−) has a decreased drain current due to the hot-carrier effect, so that the power to pull down the inverted output potential V(o−) to the ground side is weaker than that of the transistor NMmn(o+). Namely, the inverted output potential V(o−) of the flip-flop 12 is latched to the high level, and the non-inverted output potential V(o+) of the flip-flop 12 is latched to the low level.
The operations described above achieve nonvolatile storage.
[Non Patent Document 1] Enomoto Tadayoshi, “CMOS Integrated Circuit: Introduction to Specification”, Baifukan 1996
[Patent Document 1] Japanese Patent Application Publication 6-76582
The nonvolatile memory circuit shown in FIG. 3 has a problem as follows. In order to generate a hot-carrier effect in the transistor NMmn(o−) or the transistor NMmn(o+), there is a need to apply a sufficiently high voltage between the source and drain of the transistor. As described in Patent Document 1, thus, it is necessary to design the circuit such that the conductance of the transistor NMmn(o−) and the transistor NMmn(o+) is sufficiently smaller than the conductance of the transistor SWmn(o+) and the transistor SWmn(o−).
As is well known from the viewpoint of the design and optimization of SRAM, the attainment of stable operation of SRAM at the time of read operation requires a sufficient static noise margin. In order to achieve this, the circuit has to be designed such that the conductance of the transistor NMmn(o−) and the transistor NMmn(o+) is sufficiently larger than the conductance of the transistor SWmn(o+) and the transistor SWmn(o−). The optimization of such circuit design is called Static Noise Margin, which is described in detail in E. Seevinck et al. “Static-Noise Margin Analysis of MOS SRAM Cells,” IEEE Journal of Solid-state Circuits Vol. SC-22, No. 5, Oct. 1987, pp. 748-754.
The operation to transfer the information represented by the latched potentials to the bit lines is performed by placing the two bit lines in an equal potential, with the potential Vm(i) of the word line WL being set to 1.5 V to turn on the transistor SWmn(o+) and the transistor SWmn(o−). In this operation, however, if the bit lines BL+ and BL− are at the equal potential, and the transistor SWmn(o+) and the transistor SWmn(o−) are in the state of having a low ON resistance, the inverted output potential V(o−) of the flip-flop 12 and the non-inverted output potential v(o+) are pulled by the potentials of the bit lines, resulting in the destruction of the latched state stored as the potential V(o−) and the potential V(o+). Namely, an event occurs in which the restored nonvolatile data cannot be transferred stably to the outside circuit.
As described above, in respect of the nonvolatile memory circuit shown in FIG. 3, the transistor design requirements are contradictory between the write operation and the read operation.